
package cell_library is

        component AN2   -- 2 input AND
                 port(A, B : in BIT; Z : out BIT);
        end component ;

        component EO  -- 2 input XOR
                port(A, B : in BIT; Z : out BIT);
        end component ;

end cell_library;

use work.cell_library.all;
entity VHDL is
        port(
                A, B, C : in  BIT;
                Z       : out BIT
        );
end VHDL;

architecture VHDL_1 of VHDL is
        signal AB : BIT;
begin

        U1: AN2 port map(A, B, AB);
        U2: EO  port map(AB, C, Z);

end VHDL_1;


