
entity VHDL is
         port(
                A, B, C : in  BIT_VECTOR ( 1 to 5 );
                Z       : out BIT_VECTOR ( 1 to 5 )
         );
end VHDL;

architecture VHDL_1 of VHDL is
begin
         process(A,B,C)
                variable TEMP : BIT_VECTOR ( 1 to 5 );
        begin
                TEMP := A and B;
                Z    <= TEMP or C;
         end process;
end VHDL_1;



