use work.TSL_Package.all;
entity PAR_IN_SER_OUT is
        port (DATA  : in  WORD; LOAD  : in  bit; CLOCK : in  bit;  NINTO : out bit; O  : out bit);
end PAR_IN_SER_OUT;
 
architecture PAR_IN_SER_OUT_RTL of PAR_IN_SER_OUT is
        signal OREG, NEXT_OREG : bit_vector (WORD_LENGTH downto 0);
begin  -- if LOAD then parallel load, else store next state
        SEQ_PAR_IN : process(LOAD,CLOCK,DATA,NEXT_OREG)
        begin
                if (LOAD = bit' ('1')) then OREG <= (bit' ('1') & DATA);
                elsif (CLOCK'event and CLOCK = '1') then OREG <= NEXT_OREG;
                end if;
        end process;
 
        COM_PAR_IN : process(OREG)  -- compute next state, and the completion signal
                variable go : bit;
        begin
                go := bit' ('0');
                for I in WORD_LENGTH downto 1 loop
                        go := go or OREG(I);
                end loop;
                NINTO <= go;
                NEXT_OREG <= bit' ('0') & OREG(WORD_LENGTH downto 1); O <= OREG(0);        end process;
 
end PAR_IN_SER_OUT_RTL;
 
 

