
entity CLOCK_GEN is  -- Synopsys TRANSLATE_OFF
        generic (ICLK_DEL, OCLK_DEL : Time := 0 ns);  -- Synopsys TRANSLATE_ON
        port( ICLK : buffer BIT; OCLK : buffer BIT);
  end CLOCK_GEN;

architecture CLOCK_GEN_RTL of CLOCK_GEN is
                signal tmp_ICLK, tmp_OCLK : BIT;
        begin  -- Synopsys TRANSLATE_OFF
                process(tmp_ICLK,tmp_OCLK) begin
                        tmp_ICLK <= not tmp_ICLK after ICLK_DEL/4;
                        tmp_OCLK <= not tmp_OCLK after OCLK_DEL;
        end process;
        ICLK <= tmp_ICLK;
        OCLK <= tmp_OCLK;  -- Synopsys TRANSLATE_ON
end CLOCK_GEN_RTL;
 

