

-- Synopsys TRANSLATE_OFF
use work.TSL_Package.all;
        entity BTS4 is
                port( A  : in  BIT;             -- data input
                        E  : in  BIT;             -- enable
                        Z  : out wired_or BIT);   -- resolved bit data output
        end BTS4;

architecture BTS4_HDL of BTS4 is
        begin
                process (A,E)
                begin
                        if (E = '0') then Z <= '0'; -- 3stated state is zero here!!                        else Z <= A;
                        end if;
                end process;
        end BTS4_HDL;
-- Synopsys TRANSLATE_ON

use work.TSL_Package.all;
        entity BTS4_BANK is
                port( IN_WORD : in  WORD; ENABLE  : in  BIT;
                                OUT_WORD: out WORD);
        end BTS4_BANK;

architecture BTS4_BANK_RTL of BTS4_BANK is
        begin
                GEN_BANK : for I in WORD_LENGTH-1 downto 0  generate
                        U1 : BTS4 port map(IN_WORD(I), ENABLE, OUT_WORD(I));
                end generate;
        end BTS4_BANK_RTL;



