

package TSL_Package is

        constant WORD_LENGTH : integer := 8;
        subtype WORD  is BIT_VECTOR((WORD_LENGTH-1) downto 0);
        type WORD_VECTOR is array (INTEGER RANGE <> ) of WORD;

        function WIRED_OR(SOURCES: BIT_VECTOR)  return bit;
        function WIRED_OR(SOURCES: WORD_VECTOR) return WORD;
 
                component CLOCK_GEN  -- Synopsys TRANSLATE_OFF
                generic (ICLK_DEL, OCLK_DEL : Time);  - Synopsys TRANSLATE_ON
                port( ICLK : buffer BIT; OCLK : buffer BIT);
                end component;
 
                component BTS4
                port( A: in  BIT; E: in  BIT; Z: out wired_or BIT);
                end component;
 
                component BTS4_BANK
                port( IN_WORD : in  WORD; ENABLE  : in  BIT;
                                OUT_WORD: out wired_or WORD);
                end component;
 
                component PAR_IN_SER_OUT
                port (DATA: in  WORD; LOAD: in  bit; CLOCK: in  bit;
                                NINTO: out bit; O: out bit);
                end component;
 
                component SER_IN_PAR_OUT
                port (I: in  BIT; CLOCK: in  bit; NINTI: buffer bit;
                                OUTPUT: out WORD);
                end component;
 
                component UART  -- Synopsys TRANSLATE_OFF
                generic (Clk_Per,ODel,INDel,INTDel: Time := 0 ns);  -- Synopsys TRANSLATE_ON
                port ( DATA: inout WORD; I: in BIT; LOAD: in BIT; READ: in BIT;
                                O: out BIT; NINTO: out BIT; NINTI: buffer BIT);
                end component;
 
end TSL_Package;
 
 

