
entity TWO_PHASE is
        port(PHI_1, PHI_2, A: in BIT;   Z: buffer BIT);
end TWO_PHASE;

architecture DUAL_PHASE of TWO_PHASE is
        signal TEMP: BIT;
begin
        process(PHI_1,A,Z) begin
                if(PHI_1 = T1U) then
                        TEMP <= A and Z;
                end if;
        end process;

        process(PHI_2,TEMP) begin
                if(PHI_2 = T1U) then
                        Z <= not TEMP;
                end if;
        end process;
end DUAL_PHASE;


