
package s_types is
        type ENUM is (STOP, SLOW, MEDIUM, FAST);
end s_types;

use work.s_types.all;
entity VHDL is
        port(
                ACCELERATOR     : in BIT;
                BRAKE                           : in BIT;
                CLOCK                           : in BIT;
                SPEED                           : buffer ENUM
        );
end VHDL;

architecture VHDL_1 of VHDL is
begin
        process begin
                wait until not CLOCK'stable and CLOCK = '1';
                if (ACCELERATOR = '1') then
                         case SPEED is
                                when STOP =>    SPEED <= SLOW;
                                when SLOW =>    SPEED <= MEDIUM;
                                when MEDIUM =>  SPEED <= FAST;
                                when FAST =>    SPEED <= FAST;
                        end case;
                elsif (BRAKE = '1') then
                        case SPEED is
                                when STOP =>    SPEED <= STOP;
                                when SLOW =>    SPEED <= STOP;
                                when MEDIUM =>  SPEED <= SLOW;
                                when FAST =>    SPEED <= MEDIUM;
                        end case;
                else
                        -- Speed does not change
                end if;
        end process;
end VHDL_1;
 
 

