
entity VHDL is
        port(
                A, B : in  BIT_VECTOR (1 to 7);
                EQL  : out BOOLEAN
        );
end VHDL;

architecture VHDL_SMALL of VHDL is
        attribute MAX_AREA of VHDL_SMALL :  entity is 0;
begin
        EQL <=  (A = B);
end VHDL_SMALL;


architecture VHDL_FAST of VHDL is
        attribute MAX_DELAY of EQL : signal is 0;
begin
        EQL <=  (A = B);
end VHDL_FAST;



