
 
use work.SYNOPSYS.all;
use work.AMD_PACK.all;
 
entity STACK_ELEMENT is
        port( VALUE : in ADDRESS; CLOCK : in BIT;
              WRITE_ENABLE : in BIT; OUTPUT_ENABLE: in bit;
              OUTPUT: out ADDRESS);
end STACK_ELEMENT;
 
architecture STACK_ELEMENT_HDL of STACK_ELEMENT is
        component BTS5 port(A: in BIT; E: in BIT;
                 z: out BIT); end component;

        signal GATED_CLOCK: BIT;             
        signal LATCHED_VALUE : ADDRESS;
 
begin
        GATED_CLOCK <= CLOCK and WRITE_ENABLE;
 
  process
  begin
        wait until (not GATED_CLOCK'event and GATED_CLOCK = '1');
        LATCHED_VALUE <= VALUE;
  end process;
 
GEN_STACK : for I in ADDRESS_SIZE'LOW to ADDRESS_SIZE'HIGH generate
        U1: BTS5 port map(LATCHED_VALUE(I), OUTPUT_ENABLE, OUTPUT(I));
end generate;
 
end STACK_ELEMENT_HDL;
 
 
 

