
 
entity VHDL is
        port(
                ENABLE : in  BIT;
                CLOCK  : in  BIT;
                TOGGLE : buffer BIT
        );
end VHDL;
 
architecture VHDL_1 of VHDL is
begin
         process begin
                wait until not CLOCK'stable and CLOCK = '1';
                if (ENABLE = '1') then
                        TOGGLE <= not TOGGLE;
                end if;
         end process;
end VHDL_1;
 
 

