
package ops is
        subtype WORD is BIT_VECTOR (1 to 16);
        function asr(INPUT : WORD) return WORD;
end ops;

package body ops is   -- Arithmetic shift right function
        function asr(INPUT : WORD) return WORD is
                variable RESULT : WORD;
        begin
                RESULT(1)       := INPUT(1);
                RESULT(2 to 16) := INPUT(1 to 15);
                return RESULT;
        end;
end ops;


use work.ops.all;
entity VHDL is
        port(
                INPUT  : in  WORD;
                OUTPUT : out WORD
        );
end VHDL;

architecture VHDL_1 of VHDL is
begin
        OUTPUT <= asr(asr(asr(INPUT)));
end VHDL_1;
 
 

