

entity VHDL is
        port(
                WORD    : in  BIT_VECTOR ( 0 to 7 );
                PARITY  : out BIT
        );
end VHDL;

architecture VHDL_1 of VHDL is
begin
         process(WORD)
                variable RESULT : bit;
        begin
                RESULT :=  '0';
                for I in 0 to 7 loop
                        RESULT := RESULT xor WORD(I);
                end loop;
                PARITY <= RESULT;
        end process;
end VHDL_1;


