
package c_types is
        type ENUM is (USE_A, USE_B, USE_C, USE_D);
        attribute ENUM_ENCODING of ENUM : type is "00 01 10 11";
end c_types;

use work.c_types.all;
entity VHDL is
        port(
                A, B, C, D  : in  BIT;
                CHOICE      : in  ENUM;
                Z           : out BIT
        );
end VHDL;

use work.c_types.all;
architecture VHDL_1 of VHDL is
begin
        process (CHOICE) begin
                case CHOICE is
                         when USE_A =>   Z <= A;
                         when USE_B =>   Z <= B;
                         when USE_C =>   Z <= C;
                         when USE_D =>   Z <= D;
                end case;
        end process;
end VHDL_1;

