
entity VHDL is
        port(
                A, B  : in  BIT;
                USE_B : in  BIT;
                Z     : out BIT
        );
end VHDL;

architecture VHDL_1 of VHDL is
begin
         process(USE_B,B,A) begin
                 if (USE_B = '1') then
                         Z <= B;
                else
                         Z <= A;
                end if;
        end process;
end VHDL_1;



