

entity VHDL is
        port(
                A      : in BIT_VECTOR( 0 to 7 );
                OUTPUT : out BIT
        );
end VHDL;

architecture VHDL_1 of VHDL is
begin
        OUTPUT <= A( 5 );
end VHDL_1;




entity VHDL_VAR is
        port(
                A      : in BIT_VECTOR( 0 to 7 );
                INDEX  : in INTEGER range 0 to 7;
                OUTPUT : out BIT
        );
end VHDL_VAR;

architecture VHDL_1 of VHDL_VAR is
begin
        OUTPUT <= A( INDEX );
end VHDL_1;



