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--       Welcome to some switch-level VHDL descriptions
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Legal Matter:

The files in this directory can be used with the 
following restrictions:
1. Observe the export regulations of the United States 
   of America. When in doubt check with the Department of 
   Commerce, or with Alec Stanculescu (Fax: 415 578 0260).
2. Do not separate the copyright nor the notes in the header 
   of each file from the code. 
3. If you modify the code give proper credit to the previous 
   version and to whomever that version gave credit to.

Technical Matter:

All the code uses the Std_Logic package placed in the public
domain by Vantage Analysis Systems, Inc. (Tel: 415 659 0901).
If you have questions regarding the code please contact Alec
Stanculescu at Fintronic USA in Menlo Park CA, at 415 325 4474.

All models containing the word "top" in their name contain 
some stimulus to drive the simulation.

The files on the diskette are grouped in three directories: RAM, 
MEM, and ADDER.

Important Notes:
   i)  Do not use stimulus of strength 'F'. 
   ii) Do not give the generic parameter MAXSTRENGTH of the bi-directional 
switch (bxfr) the value 'F'.
   iii) One way of changing from using configurations to not using 
them is: 
     (a) change the names of the components by appending "_type" to 
them. Make sure that you update the references to the component for all 
instantiations.
     (b) add one configuration after each entity/architecture pair,
     (c) refer in each  higher level configuration to the lower level
configurations,
   iv) One way of changing from not using configurations to using 
them is: 
     (a) change the names of the components to match the names of the entity
to which it must be associated. Make sure that you update the references
to the component for all instantiations.
     (b) remove all configurations.

1. RAM directory

This directory contains: sw_old.vhd, sw_new.vhd,
and ram.vhd.

Note: files in this directory make use of configurations.

The files sw_old.vhd and sw_new.vhd contain VHDL 
decriptions of bi-directional switches (nfet, and pfet),
that are based on the same architecture: bxfr_behavior.
Each file contains a different version of bxfr_behavior. Both
versions work. The version in sw_new.vhd is faster and easier to
comprehend. The version in sw_old.vhd is presented in the book.
Alec Stanculescu and Bob Sahai developed the second version while 
trying to prove that the first version behaved correctly. The authors 
believe that the two versions are equivalent in the sense that they 
produce the same signal values at the end of each timepoint.

One of the files sw_old.vhd and sw_new.vhd must be 
compiled along with the std_logic package before compiling
ram.vhd (memory element described in book, where
path-transistors have different strengths). 

2. MEM directory

This directory contains the following files: std_l.vhd, sw.vhd,
invert.vhd, mem.vhd, and mem_top.vhd. These files must be 
compiled in this precise order. 

Note: files in this directory do not use configurations.

The file std_l.vhd contains a truncated version of the std_logic 
package.

The file sw.vhd contains a version of sw_old.vhd that does not need 
configurations.

The file mem.vhd contains the description of the example in the book.

The file mem_top.vhd conntains stimulus for the model contained in the
file mem.vhd.

3. ADDER directory

This directory contains the following files: sw.vhd, nand2.vhd, adder1.vhd, 
adder2.vhd, adder4.vhd, adder6.vhd. These files must be compiled
in this order.

Note: files in this directory do not use configurations.